DFiant HDL Docs (DFDocs)🔗
The Official DFiant Hardware Description Language (HDL) Documentation
Welcome to the DFiant hardware description language (HDL) documentation!
DFiant is a dataflow HDL and is embedded as a library in the Scala programming language. DFiant enables timing-agnostic and device-agnostic hardware description by using dataflow firing rules as logical constructs, coupled with modern software language features (e.g., inheritance, polymorphism) and classic HDL features (e.g., bit-accuracy, input/output ports).
By this point you may already have some questions:
- Why do we need yet another HDL?
- Why are high-level synthesis (HLS) tools not enough?
- What is a dataflow HDL?
Answers to these questions await you at the linked sections.
But, if you're curious about the DFiant language, checkout our first-look section first.
You are not required to know Scala, yet you are expected to understand basic object oriented concepts. This documentation attempts to bridge over any syntactic gaps you may arrive at. Nonetheless, as you attempt to create more complex and generic designs, more Scala knowledge will be required of you.
You are not required to be an FPGA/ASIC expert, yet you are expected to understand fundamental hardware description concepts found in languages such as Verilog and VHDL.
You are required to keep an open mind. Some of these concepts may seem strange at first, but they were set after careful thought and planning. However, we are not infallible so feel free to file an issue with questions and/or suggestions of different approaches we can take.