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DFiant HDL (DFHDL) Docs

The Official DFiant Hardware Description Language (DFHDL) Documentation


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Welcome to the DFiant hardware description language (DFHDL) documentation!

DFHDL is a dataflow HDL and is embedded as a library in the Scala programming language. DFiant enables timing-agnostic and device-agnostic hardware description by using dataflow firing rules as logical constructs, coupled with modern software language features (e.g., inheritance, polymorphism, pattern matching) and classic HDL features (e.g., bit-accuracy, input/output ports). Additionally, DFHDL integrates two additional levels of hardware description abstractions: register-transfer (RT), which is equivalent to languages like Chisel and Amaranth; and event-driven (ED), which is equivalent to Verilog and VHDL.

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Documentation Status

We are actively working on a comprehensive user guide. We hope to be releasing it in the coming days.

In the meanwhile, checkout our getting-started guide, to setup your system and try out a basic example. Additionally, we placed several examples under the Run In Browser section of the documentation, where you can try them right now.

Required Knowledge

You are not required to know Scala, yet you are expected to understand basic object oriented concepts. This documentation attempts to bridge over any syntactic gaps you may arrive at. Nonetheless, as you attempt to create more complex and generic designs, more Scala knowledge will be required of you.

You are not required to be an FPGA/ASIC expert, yet you are expected to understand fundamental hardware description concepts found in languages such as Verilog and VHDL.

You are required to keep an open mind. Some of these concepts may seem strange at first, but they were set after careful thought and planning. However, we are not infallible so feel free to file an issue with questions and/or suggestions of different approaches we can take.